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fujitsu microelectronics data sheet copyright?2008-2009 fujitsu microelec tronics limited all rights reserved 2009.6 8-bit microcontroller cmos f 2 mc-8fx mb95220h series MB95F222H/f223h mb95f222k/f223k description mb95220h are a series of general-purpose, single-chip mi crocontrollers. in addition to a compact instruction set, the microcontrollers of these series c ontain a variety of peripheral resources. note: f 2 mc is the abbreviation of fujitsu flexible microcontroller. features ? f 2 mc-8fx cpu core instruction set optimized for controllers ? multiplication and division instructions ? 16-bit arithmetic operations ? bit test branch instructions ? bit manipulation instructions, etc. ? clock ? selectable main clock source external clock (up to 32.5 mhz, maxi mum machine clock frequency: 16.25 mhz) main internal cr clock (1/8/10 mhz 3%, maximum machine clock frequency: 10 mhz) ? selectable subclock source external clock (32.768 khz) sub-internal cr clock (typ: 100 khz, min: 50 khz, max: 200 khz) ? timer ? 8/16-bit composite timer ? timebase timer ? watch prescaler ? lin-uart (MB95F222H/f222k/f223h/f223k) ? full duplex double buffer ? capable of clock-synchronized serial data transf er and clock-asynchronized serial data transfer (continued) ds07-12626-2e
mb95220h series 2 ds07-12626-2e (continued) ? external interrupt ? interrupt by edge detection (rising edge , falling edge, and both edges can be selected) ? can be used to wake up the device from different low power consumption (standby) modes ? 8/10-bit a/d converter ? 8-bit or 10-bit resolution can be selected. ? low power consumption (standby) modes ? stop mode ? sleep mode ? watch mode ? timebase timer mode ? i/o port (max: 13) (mb95f222k/f223k) ? general-purpose i/o ports (max): cmos i/o: 11, n-ch open drain: 2 ? i/o port (max: 12 ) (MB95F222H/f223h) ? general-purpose i/o ports (max): cmos i/o: 11, n-ch open drain: 1 ? on-chip debug ? 1-wire serial control ? serial writing suppor ted (asynchronous mode) ? hardware/software watchdog timer ? built-in hardware watchdog timer ? low-voltage detection reset circuit ? built-in low-voltage detector ? clock supervisor counter ? built-in clock supervisor counter function ? programmable port input voltage level ? cmos input level / hysteresis input level ? flash memory security function ? protects the contents of flash memory
mb95220h series ds07-12626-2e 3 product line-up (continued) part number parameter mb95f223h MB95F222H mb95f223k mb95f222k type flash memory product clock supervisor counter it supervises the main clock oscillation. rom capacity 8 kb 4 kb 8 kb 4 kb ram capacity 496 b 240 b 496 b 240 b low-voltage detection reset no yes reset input dedicated selected by software cpu functions number of basic instructions : 136 instruction bit length : 8 bits instruction length : 1 to 3 bytes data bit length : 1, 8, and 16 bits minimum instruction execution time : 61.5 ns (with machine clock = 16.25 mhz) interrupt processing time : 0.6 s (with machine clock = 16.25 mhz) general- purpose i/o i/o ports (max): 12 cmos: 11, n-ch: 1 i/o ports (max): 13 cmos: 11, n-ch: 2 timebase timer interrupt cycle : 0.256 ms - 8.3 s (when external clock = 4 mhz) hardware/ software watchdog timer reset generation cycle main oscillation clock at 10 mhz : 105 ms (min) the sub-internal cr clock can be used as the source clock of the hardware watchdog timer. wild register it can be used to replace three bytes of data. lin-uart a wide range of communication speed can be selected by a dedicated reload timer. it has a full duplex double buffer. clock-synchronized serial data transfer and clock-asynchronized serial data transfer is enabled. the lin function can be used as a lin master or a lin slave. 8/10-bit a/d converter 5 ch. 8-bit or 10-bit resolution can be selected. 8/16-bit composite timer 1 ch. the timer can be configured as an "8-bit time r x 2 channels" or a "16-bit timer x 1 channel". it has built-in timer function, pwc function , pwm function and input capture function. count clock: it can be selected from intern al clocks (seven types) and external clocks. it can output square wave. external interrupt 6 ch. interrupt by edge detection (the rising edge, falling edge, or both edges can be selected.) it can be used to wake up the device from standby modes. on-chip debug 1-wire serial control it supports serial writing. (asynchronous mode)
mb95220h series 4 ds07-12626-2e (continued) part number parameter mb95f223h MB95F222H mb95f223k mb95f222k watch prescaler eight different time intervals can be selected. flash memory it supports automatic programming, embedded algorithm, write/erase/erase-suspend/erase-resume commands. it has a flag indicating the completion of the operat ion of embedded algorithm. number of write/erase cycles (min): 100000 data retention time: 20 years for write/erase, external vpp(+10 v) input is required. flash security feature for protecting the contents of the flash standby mode sleep mode, stop mode , watch mode, timebase timer mode package dip-16p-m06 fpt-16p-m06
mb95220h series ds07-12626-2e 5 packages and corresponding products o: available part number package mb95f223h MB95F222H mb95f223k mb95f222k dip-16p-m06oooo fpt-16p-m06oooo
mb95220h series 6 ds07-12626-2e differences among products and notes on product selection ? current consumption when using the on-chip debug function, take account of the current consumption of flash erase/program. for details of current consumption, see ? electrical characteristics?. ? package for details of information on each package, see ? packages and corresponding products? and ? package dimensions?. ? operating voltage the operating voltage varies, depending on whethe r the on-chip debug function is used or not. for details of the operating voltage, see ? electrical characteristics?. ? on-chip debug function the on-chip debug function requires that v cc , v ss and 1 serial-wire be connected to an evaluation tool. in addition, if the flash memory data has to be updated, the rst /pf2 pin must also be connect ed to the same evaluation tool.
mb95220h series ds07-12626-2e 7 pin assignment p12/ec0/dbg p07/int07 p06/int06/to01 p05/int05/an05/to00/hclk2 p04/int04/an04/sin/hclk1/ec0 p03/int03/an03/sot p01/an01 p02/int02/an02/sck x0/pf0 x1/pf1 vss x1a/pg2 x0a/pg1 vcc rst/pf2 c (top view) 16 pins 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8
mb95220h series 8 ds07-12626-2e pin description (mb95220h series) (continued) pin no. pin name i/o circuit type* function 1 pf0 b general-purpose i/o port x0 main clock input oscillation pin 2 pf1 b general-purpose i/o port x1 main clock i/o oscillation pin 3v ss ? power supply pin (gnd) 4 pg2 c general-purpose i/o port x1a subclock i/o oscillation pin 5 pg1 c general-purpose i/o port x0a subclock input oscillation pin 6v cc ? power supply pin 7 pf2 a general-purpose i/o port rst reset pin this pin is a dedicated reset pin in MB95F222H/f223h. 8 c ? capacitor connection pin 9 p02 e general-purpose i/o port int02 external interrupt input pin an02 a/d converter analog input pin sck lin-uart clock i/o pin 10 p01 e general-purpose i/o port an01 a/d converter analog input pin 11 p03 e general-purpose i/o port int03 external interrupt input pin an03 a/d converter analog input pin sot lin-uart data output pin 12 p04 f general-purpose i/o port int04 external interrupt input pin an04 a/d converter analog input pin sin lin-uart data input pin hclk1 external clock input pin ec0 8/16-bit composite timer ch. 0 clock input pin
mb95220h series ds07-12626-2e 9 (continued) *: for the i/o circuit types, see " i/o circuit type". pin no. pin name i/o circuit type* function 13 p05 e general-purpose i/o port high-current port int05 external interrupt input pin an05 a/d converter analog input pin to00 8/16-bit composite timer ch. 0 clock input pin hclk2 external clock input pin 14 p06 g general-purpose i/o port high-current port int06 external interrupt input pin to01 8/16-bit composite timer ch. 0 clock input pin 15 p07 g general-purpose i/o port int07 external interrupt input pin 16 p12 h general-purpose i/o port ec0 8/16-bit composite timer ch. 0 clock input pin dbg dbg input pin
mb95220h series 10 ds07-12626-2e i/o circuit type (continued) type circuit remarks a ? n-ch open drain output ? hysteresis input ? reset output b ? oscillation circuit ? high-speed side feedback resistance: approx. 1 m ? cmos output ? hysteresis input c ? oscillation circuit ? low-speed side feedback resistance: approx. 10 m ? cmos output ? hysteresis input ? pull-up control available n-ch reset output / digital output reset input / hysteresis output s tandby control / port select clock input port select digital output digital output s tandby control hysteresis input digital output digital output s tandby control hysteresis input port select x1 x0 n-ch p-ch n-ch p-ch clock input x1a x0a s tandby control / port select n-ch p-ch port select digital output digital output s tandby control hysteresis input n-ch digital output digital output digital output s tandby control hysteresis input p-ch r pull-up control port select p-ch r pull-up control
mb95220h series ds07-12626-2e 11 (continued) type circuit remarks d ?cmos output ? hysteresis input e ?cmos output ? hysteresis input ? pull-up control available f ?cmos output ? hysteresis input ? cmos input ? pull-up control available g ? hysteresis input ?cmos output ? pull-up control available h ? n-ch open drain output ? hysteresis input n-ch p-ch digital output digital output s tandby control hysteresis input n-ch p-ch p-ch r pull-up control digital output digital output analog input a/d control s tandby control hysteresis input n-ch p-ch p-ch r pull-up control digital output digital output analog input a/d control s tandby control hysteresis input cmos input n-ch p-ch p-ch r pull-up control digital output digital output s tandby control hysteresis input n-ch s tandby control hysteresis input digital output
mb95220h series 12 ds07-12626-2e notes on device handling ? preventing latch-ups when using the device, ensure that the voltage applied does not exce ed the maximum voltage rating. in a cmos ic, if a voltage higher than v cc or a voltage lower than v ss is applied to an input/output pin that is neither a medium-withstand vo ltage pin nor a high-withstand voltage pin, or if a voltage out of the rating range of power supply voltage mentioned in 1. absolute maximum ratings of electrical characteristics? is applied to the v cc pin or the v ss pin, a latch-up may occur. when a latch-up occurs, power supply current increases significantly, which may cause a component to be thermally destroyed. ? stabilizing supply voltage supply voltage must be stabilized. a malfunction may occur when power supp ly voltage fluctuates rapidly even t hough the fluctuation is within the guaranteed operating range of the v cc power supply voltage. as a rule of voltage stabilizatio n, suppress voltage fluctuation so that the fluctuation in v cc ripple (p-p value) at the commercial frequency (50 hz/60 hz) does not exceed 10% of the standard v cc value, and the transient fluctuation rate does not exceed 0.1 v/ms at a moment ary fluctuation such as switching the power supply. ? notes on using the external clock when an external clock is used, oscilla tion stabilization wait time is required for power-on reset, wake-up from subclock mode or stop mode. pin connection ? treatment of unused pins if an unused input pin is left unconnected, a compon ent may be permanently damaged due to malfunctions or latch-ups. always pull up or pull down an unused input pin through a resistor of at least 2 k . set an unused input/output pin to the output state and leave it unconnected, or set it to the input state and treat it the same as an unused input pin. if there is an unused output pin, leave it unconnected. ? power supply pins to reduce unnecessary electro-magnetic emission, preven t malfunctions of strobe signals due to an increase in the ground level, and conform to the tota l output current standard, always connect the v cc pin and the v ss pin to the power supply and ground outside the device. in addition, connect the current supply source to the v cc pin and the v ss pin with low impedance. it is also advisable to connect a ceramic capacitor of approximately 0.1 f as a bypass capacitor between the v cc pin and the v ss pin at a location close to this device. ? dbg pin connect the dbg pin directly to an external pull-up resistor. to prevent the device from unintentionally entering the debug mode due to noise, minimize the distance between the dbg pin and the v cc or v ss pin when designing the layout of the printed circuit board. the dbg pin should not stay at ?l? level af ter power-on until the reset output is released. ? rst pin connect the rst pin directly to an external pull-up resistor. to prevent the device from unintentionally entering the reset mode due to noise, minimize the distance between the rst pin and the v cc or v ss pin when designing the layout of the printed circuit board. the rst /pf2 pin functions as the reset input/output pin afte r power-on. in addition, th e reset output of the rst / pf2 pin can be enabled by the rstoe bit of the sysc r egister, and the reset input function and the general purpose i/o function can be selected by the rsten bit of the sysc register.
mb95220h series ds07-12626-2e 13 ? c pin use a ceramic capacitor or a capacitor with equivalent frequency characteristics. the bypass capacitor for the v cc pin must have a capacitance larger than c s . for the connection to a smoothing capacitor c s , see the diagram below. to prevent the device from unintentionally entering a mode to which the device is not set to transit due to noise, minimize the distance between the c pin and c s and the distance between c s and the v ss pin when designing the layout of a printed circuit board. c cs dbg rst ? dbg/rst /c pin connection diagram
mb95220h series 14 ds07-12626-2e block diagram (mb95220h series) flash with security function (8/4 kb) ram (496/240 b) interrupt controller 8 /10-bit a/d converter 8/16-bit composite timer (0) res et with lvd oscillator circuit cr oscillator clock control on-chip debu g wild register external interrupt lin-uart port port f 2 mc-8fx cpu internal bus (p05 *3 /to00) (p06 *3 /to01) p12 *1 /ec0, (p04/ec0) (p01/an01-p05 *3 /an05) pf1/x1 *2 pf0/x0 *2 pg2/x1a *2 pg1/x0a *2 (p04/hclk1) (p05 *3 /hclk2) (p12/dbg) p02/int02-p07/int07 (p02/sck) (p03/s ot) (p04/sin) c v cc v ss * 1: pf2 and p12 are nch open dr ain pins . * 2: softw are option *3 : p05 and p06 are high-cu rrent ports . pf2 *1 /rst *2
mb95220h series ds07-12626-2e 15 cpu core ? memory space the memory space of the mb95220h series is 64 kb in size, and consists of an i/o area, a data area, and a program area. the memory space includes areas inte nded for specific purposes such as general-purpose registers and a vector table. the memory ma ps of the mb95220h series are shown below. ? memory maps i/o 0000 h 0080 h access prohibited 0090 h ram 496 b 0280 h register 0100 h 0200 h access prohibited extension i/o 0f80 h 1000 h access prohibited e000 h flash 8 kb i/o access prohibited ram 240 b register access prohibited extension i/o access prohibited flash 4 kb ffff h 0000 h 0080 h 0090 h 0100 h 0180 h 0f80 h 1000 h f000 h ffff h mb95f223h/f223k MB95F222H/f222k
mb95220h series 16 ds07-12626-2e i/o map (mb95220h series) (continued) address register abbreviation register name r/w initial value 0000 h pdr0 port 0 data register r/w 00000000 b 0001 h ddr0 port 0 direction register r/w 00000000 b 0002 h pdr1 port 1 data register r/w 00000000 b 0003 h ddr1 port 1 direction register r/w 00000000 b 0004 h ? (disabled) ? ? 0005 h watr oscillation stabilization wait time setting register r/w 11111111 b 0006 h ? (disabled) ? ? 0007 h sycc system clock control register r/w 0000x011 b 0008 h stbc standby control register r/w 00000xxx b 0009 h rsrr reset source register r xxxxxxxx b 000a h tbtc timebase timer control register r/w 00000000 b 000b h wpcr watch prescaler control register r/w 00000000 b 000c h wdtc watchdog timer control register r/w 00000000 b 000d h sycc2 system clock control register 2 r/w xx100011 b 000e h to 0015 h ? (disabled) ? ? 0016 h ? (disabled) ? ? 0017 h ? (disabled) ? ? 0018 h to 0027 h ? (disabled) ? ? 0028 h pdrf port f data register r/w 00000000 b 0029 h ddrf port f direction register r/w 00000000 b 002a h pdrg port g data register r/w 00000000 b 002b h ddrg port g direction register r/w 00000000 b 002c h pul0 port 0 pull-up register r/w 00000000 b 002d h to 0034 h ? (disabled) ? ? 0035 h pulg port g pull-up register r/w 00000000 b 0036 h t01cr1 8/16-bit composite timer 01 stat us control register 1 ch. 0 r/w 00000000 b 0037 h t00cr1 8/16-bit composite timer 00 stat us control register 1 ch. 0 r/w 00000000 b 0038 h ? (disabled) ? ? 0039 h ? (disabled) ? ? 003a h to 0048 h ? (disabled) ? ? 0049 h eic10 external interrupt circuit cont rol register ch. 2/ch. 3 r/w 00000000 b
mb95220h series ds07-12626-2e 17 (continued) address register abbreviation register name r/w initial value 004a h eic20 external interrupt circuit cont rol register ch. 4/ch. 5 r/w 00000000 b 004b h eic30 external interrupt circuit cont rol register ch. 6/ch. 7 r/w 00000000 b 004c h to 004f h ? (disabled) ? ? 0050 h scr lin-uart serial control register r/w 00000000 b 0051 h smr lin-uart serial mode register r/w 00000000 b 0052 h ssr lin-uart serial status register r/w 00001000 b 0053 h rdr/tdr lin-uart receive/transmit data register r/w 00000000 b 0054 h escr lin-uart extended status control register r/w 00000100 b 0055 h eccr lin-uart extended communication control register r/w 000000xx b 0056 h to 006b h ? (disabled) ? ? 006c h adc1 8/10-bit a/d converter control register 1 r/w 00000000 b 006d h adc2 8/10-bit a/d converter control register 2 r/w 00000000 b 006e h addh 8/10-bit a/d converter da ta register (upper) r/w 00000000 b 006f h addl 8/10-bit a/d converter da ta register (lower) r/w 00000000 b 0070 h , 0071 h ? (disabled) ? ? 0072 h fsr flash memory status register r/w 000x0000 b 0073 h to 0075 h ? (disabled) ? ? 0076 h wren wild register address co mpare enable register r/w 00000000 b 0077 h wror wild register data test setting register r/w 00000000 b 0078 h ? mirror of register bank pointe r (rp) and direct bank pointer (dp) ?? 0079 h ilr0 interrupt level setting register 0 r/w 11111111 b 007a h ilr1 interrupt level setting register 1 r/w 11111111 b 007b h ilr2 interrupt level setting register 2 r/w 11111111 b 007c h ? (disabled) ? ? 007d h ilr4 interrupt level setting register 4 r/w 11111111 b 007e h ilr5 interrupt level setting register 5 r/w 11111111 b 007f h ? (disabled) ? ? 0f80 h wrarh0 wild register address setti ng register (upper) ch. 0 r/w 00000000 b
mb95220h series 18 ds07-12626-2e (continued) address register abbreviation register name r/w initial value 0f81 h wrarl0 wild register address setti ng register (lower) ch. 0 r/w 00000000 b 0f82 h wrdr0 wild register data setting register ch. 0 r/w 00000000 b 0f83 h wrarh1 wild register address setti ng register (upper) ch. 1 r/w 00000000 b 0f84 h wrarl1 wild register address setti ng register (lower) ch. 1 r/w 00000000 b 0f85 h wrdr1 wild register data setting register ch. 1 r/w 00000000 b 0f86 h wrarh2 wild register address setti ng register (upper) ch. 2 r/w 00000000 b 0f87 h wrarl2 wild register address setti ng register (lower) ch. 2 r/w 00000000 b 0f88 h wrdr2 wild register data setting register ch. 2 r/w 00000000 b 0f89 h to 0f91 h ? (disabled) ? ? 0f92 h t01cr0 8/16-bit composite timer 01 stat us control register 0 ch. 0 r/w 00000000 b 0f93 h t00cr0 8/16-bit composite timer 00 stat us control register 0 ch. 0 r/w 00000000 b 0f94 h t01dr 8/16-bit composite timer 01 data register ch. 0 r/w 00000000 b 0f95 h t00dr 8/16-bit composite timer 00 data register ch. 0 r/w 00000000 b 0f96 h tmcr0 8/16-bit composite timer 00/01 timer mode control register ch. 0 r/w 00000000 b 0f97 h ? (disabled) ? ? 0f98 h ? (disabled) ? ? 0f99 h ? (disabled) ? ? 0f9a h ? (disabled) ? ? 0f9b h ? (disabled) ? ? 0f9c h to 0fbb h ? (disabled) ? ? 0fbc h bgr1 lin-uart baud rate gener ator register 1 r/w 00000000 b 0fbd h bgr0 lin-uart baud rate gener ator register 0 r/w 00000000 b 0fbe h to 0fc2 h ? (disabled) ? ? 0fc3 h aidrl a/d input disable register (lower) r/w 00000000 b 0fc4 h to 0fe3 h ? (disabled) ? ? 0fe4 h crth main cr clock trimming register (upper) r/w 1xxxxxxx b 0fe5 h crtl main cr clock trimming register (lower) r/w 000xxxxx b
mb95220h series ds07-12626-2e 19 (continued) ? r/w access symbols ? initial value symbols note: do not write to an address that is ?(disabled)?. if a ?(disabled)? address is read, an undefined value is returned. address register abbreviation register name r/w initial value 0fe6 h , 0fe7 h ? (disabled) ? ? 0fe8 h sysc system configuration register r/w 11000011 b 0fe9 h cmcr clock monitoring control register r/w 00000000 b 0fea h cmdr clock monitoring data register r/w 00000000 b 0feb h wdth watchdog timer selection id register (upper) r/w xxxxxxxx b 0fec h wdtl watchdog timer selection id register (lower) r/w xxxxxxxx b 0fed h ? (disabled) ? ? 0fee h ilsr input level select register r/w 00000000 b 0fef h to 0fff h ? (disabled) ? ? r/w : readable / writable r : read only w : write only 0 : the initial value of this bit is ?0?. 1 : the initial value of this bit is ?1?. x : the initial value of this bit is undefined.
mb95220h series 20 ds07-12626-2e interrupt source table (mb95220h series) interrupt source interrupt request number vector table address bit name of interrupt level setting register priority order of interrupt sourc- es of the same level (occurring simultaneously) upper lower external interrupt ch. 4 irq0 fffa h fffb h l00 [1:0] high external interrupt ch. 5 irq1 fff8 h fff9 h l01 [1:0] external interrupt ch. 2 irq2 fff6 h fff7 h l02 [1:0] external interrupt ch. 6 external interrupt ch. 3 irq3 fff4 h fff5 h l03 [1:0] external interrupt ch. 7 ?irq4fff2 h fff3 h l04 [1:0] 8/16-bit composite timer ch. 0 (lower) irq5 fff0 h fff1 h l05 [1:0] 8/16-bit composite timer ch. 0 (upper) irq6 ffee h ffef h l06 [1:0] lin-uart (reception) irq7 ffec h ffed h l07 [1:0] lin-uart (transmission) irq8 ffea h ffeb h l08 [1:0] ?irq9ffe8 h ffe9 h l09 [1:0] ?irq10ffe6 h ffe7 h l10 [1:0] ?irq11ffe4 h ffe5 h l11 [1:0] ?irq12ffe2 h ffe3 h l12 [1:0] ?irq13ffe0 h ffe1 h l13 [1:0] ? irq14 ffde h ffdf h l14 [1:0] ? irq15 ffdc h ffdd h l15 [1:0] ? irq16 ffda h ffdb h l16 [1:0] ?irq17ffd8 h ffd9 h l17 [1:0] 8/10-bit a/d converter irq18 ffd6 h ffd7 h l18 [1:0] timebase timer irq19 ffd4 h ffd5 h l19 [1:0] watch prescaler irq20 ffd2 h ffd3 h l20 [1:0] ?irq21ffd0 h ffd1 h l21 [1:0] ? irq22 ffce h ffcf h l22 [1:0] flash memory irq23 ffcc h ffcd h l23 [1:0] low
mb95220h series ds07-12626-2e 21 electrical characteristics 1. absolute maximum ratings (continued) parameter symbol rating unit remarks min max power supply voltage* 1 v cc v ss ? 0.3 v ss +6v input voltage* 1 v i v ss ? 0.3 v ss + 6v*2 output voltage* 1 v o v ss ? 0.3 v ss + 6v*2 maximum clamp current i clamp -2 +2 ma applicable to specific pins *3 total maximum clamp current |i clamp | ? 20 ma applicable to specific pins *3 ?l? level maximum output current i ol1 ? 15 ma other than p05, p06 i ol2 15 p05, p06 ?l? level average current i olav1 ? 4 ma other than p05, p06 average output current = operating current operating ratio (1 pin) i olav2 12 p05, p06 average output current = operating current operating ratio (1 pin) ?l? level total maximum output current i ol ? 100 ma ?l? level total average output current i olav ?50ma total average output current = operating current operating ratio (total number of pins) ?h? level maximum output current i oh1 ? -15 ma other than p05, p06 i oh2 -15 p05, p06 ?h? level average current i ohav1 ? -4 ma other than p05, p06 average output current = operating current operating ratio (1 pin) i ohav2 -8 p05, p06 average output current = operating current operating ratio (1 pin) ?h? level total maximum output current i oh ?-100ma ?h? level total average output current i ohav ?-50ma total average output current = operating current operating ratio (total number of pins) power consumption pd ? 320 mw operating temperature t a -40 +85 c storage temperature tstg -55 +150 c
mb95220h series 22 ds07-12626-2e (continued) *1: the parameter is based on v ss = 0.0 v. *2: v i and v o must not exceed v cc + 0.3 v. v i must not exceed the rated voltage. however, if the maximum current to/from an input is limited by means of an external component, the i clamp rating is used instead of the v i rating. *3: applicable to the following pins: p01 to p07, pg1, pg2, pf0, pf1 ? use under recommended operating conditions. ? use with dc voltage (current). ? the hv (high voltage) signal is an input signal exceeding the v cc voltage. always connect a limiting resistor between the hv (high voltage) sign al and the microcontroller before applying the hv (high voltage) signal. ? the value of the limiting resistor should be set to a valu e at which the current to be input to the microcontroller pin when the hv (high voltage) signal is input is below the standard value, irrespective of whether the current is transient current or stationary current. ? when the microcontroller drive current is low, such as in low power consumption modes, the hv (high voltage) input potential may pass through the protecti ve diode to increase the potential of the v cc pin, affecting other devices. ? if the hv (high voltage) signal is input when the microc ontroller power supply is off (not fixed at 0 v), since power is supplied from the pins, in complete operations may be executed. ? if the hv (high voltage) input is input after power-on, since power is supplied from the pins, the voltage of power supply may not be sufficient to enable a power-on reset. ? do not leave the hv (high voltage) input pin unconnected. ? example of a recommended circuit: warning: semiconductor devices can be permanently dama ged by application of stress (voltage, current, temperature, etc.) in excess of absolute ma ximum ratings. do not exceed these ratings. hv(high volt age) inpu t (0 v to 16 v) protective diode v cc n-ch p-ch r limiting resistor ? input/output equivalent circuit
mb95220h series ds07-12626-2e 23 2. recommended operating conditions (v ss = 0.0 v) *1: the value varies depending on the operating frequency, the machine clock and the analog guaranteed range. *2: the value is 2.88 v when the lo w-voltage detection reset is used. *3: use a ceramic capacitor or a capacitor with equivalent frequency characteristics. the bypass capacitor for the v cc pin must have a capacitance larger than c s . for the connection to a smoothing capacitor c s , see the diagram below. to prevent the device from unintentionally enter ing an unknown mode due to noise, minimize the distance between the c pin and c s and the distance between c s and the v ss pin when designing the layout of a printed circuit board. warning: the recommended operating co nditions are required in order to ensure the normal operation of the semiconductor device. all of the device's el ectrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operat ing conditions, or combinations not represented on the data sheet. users considering application outs ide the listed conditions are advised to contact their representatives beforehand. parameter symbol value unit remarks min max power supply voltage v cc 2.4* 1 * 2 5.5* 1 v in normal operation other than on-chip debug mode 2.3 5.5 hold condition in stop mode 2.9 5.5 in normal operation on-chip debug mode 2.3 5.5 hold condition in stop mode smoothing capacitor c s 0.022 1 f *3 operating temperature t a -40 +85 c other than on-chip debug mode +5 +35 on-chip debug mode c cs dbg * since the dbg pin becomes a comm unication pin in on-chip de bu g mode, set a pull-up resistor v alue suiting the input/output specifications of p12/dbg. *: rst ?dbg / rst / c pin connection diagram
mb95220h series 24 ds07-12626-2e 3. dc characteristics (v cc = 5.0 v 10 % , v ss = 0.0 v, t a = - 40 c to + 85 c) (continued) parameter symbol pin name condition value unit remarks min typ max "h" level input voltage v ihi p04 *1 0.7 v cc ?v cc + 0.3 v when cmos input level (hysteresis input) is selected v ihs p01 to p07, p12, pf0, pf1, pg1, pg2 *1 0.8 v cc ?v cc + 0.3 v hysteresis input v ihm pf2 ? 0.7 v cc ?v cc + 0.3 v hysteresis input ?l? level input voltage v il p04 *1 v ss ? 0.3 ? 0.3 v cc v when cmos input level (hysteresis input) is selected v ils p01 to p07, p12, pf0, pf1, pg1, pg2 *1 v ss ? 0.3 ? 0.2 v cc v hysteresis input v ilm pf2 ? v ss ? 0.3 ? 0.3 v cc v hysteresis input open-drain output application voltage v d pf2, p12 ? v ss ? 0.3 ? 0.2 v cc v ?h? level output voltage v oh1 output pins other than p05, p06, p12, pf2 i oh = -4 ma v cc ? 0.5 ? ? v v oh2 p05, p06 i oh = -8 ma v cc ? 0.5 ? ? v ?l? level output voltage v ol1 output pins other than p05, p06 i ol = 4 ma ? ? 0.4 v v ol2 p05, p06 i ol = 12 ma ? ? 0.4 v input leak current (hi-z output leak current) i li all input pins 0.0 v < v i < v cc -5 ? +5 a when pull-up resistance is disabled pull-up resistance r pull p01 to p07, pg1, pg2 v i = 0 v 25 50 100 k when pull-up resistance is enabled input capacitance c in other than v cc and v ss f = 1 mhz ? 5 15 pf
mb95220h series ds07-12626-2e 25 (v cc = 5.0 v 10 % , v ss = 0.0 v, t a = - 40 c to + 85 c) (continued) parameter symbol pin name condition value unit remarks min typ max power supply current* 2 i cc v cc (external clock operation) v cc = 5.5 v f ch = 32 mhz f mp = 16 mhz main clock mode (divided by 2) ?1317ma flash memory product (except writing and erasing) ? 33.5 39.5 ma flash memory product (at writing and erasing) ? 15 21 ma at a/d conversion i ccs v cc = 5.5 v f ch = 32 mhz f mp = 16 mhz main sleep mode (divided by 2) ?5.5 9ma i ccl v cc = 5.5 v f cl = 32 khz f mpl = 16 khz subclock mode (divided by 2) t a = +25 c ?65153a i ccls v cc = 5.5 v f cl = 32 khz f mpl = 16 khz subsleep mode (divided by 2) t a = +25 c ?1084a i cct v cc = 5.5 v f cl = 32 khz watch mode main stop mode t a = +25 c ? 5 30 a i ccmcr v cc v cc = 5.5 v f crh = 10 mhz f mp = 10 mhz main cr clock mode ?8.6?ma i ccscr v cc = 5.5 v sub-cr clock mode (divided by 2) t a = +25 c ? 110 410 a
mb95220h series 26 ds07-12626-2e (continued) (v cc = 5.0 v 10 % , v ss = 0.0 v, t a = - 40 c to + 85 c) *1: the input level of p04 can be switc hed between ?cmos input level? and ?hysteresis input level?. the input level selection register (ilsr) is used to switch between the two input levels. *2: ? the power supply current is determined by the exte rnal clock. when the low-voltage detection option is selected, the power-supply current will be the sum of adding the current consumption of the low-voltage detection circuit (i lv d ) to one of the value from i cc to i cch . in addition, when both the low-voltage detection option and the internal cr oscillator are sele cted, the power supply current will be the sum of adding up the current consumption of the low-voltage detection circuit, the cu rrent consumption of the internal cr oscillators (i crh , i crl ) and a specified value. in on-chip debug mode, the internal cr oscillator (i crh ) and the low-voltage detection circuit are always enabled, and current co nsumption therefore increases accordingly. ? see "4. ac characteristics: (1) clock timing" for f ch and f cl . ? see "4. ac characteristics: (2) source clock/machine clock" for f mp and f mpl . parameter symbol pin name condition value unit remarks min typ max power supply current* 2 i ccts v cc (external clock operation) v cc = 5.5 v f ch = 32 mhz timebase timer mode t a = +25 c ?1.1 3ma i cch v cc = 5.5 v substop mode t a = +25 c ? 3.5 22.5 a main stop mode for single clock selection i lvd v cc current consumption for low-voltage detection circuit only ?3754a i crh current consumption for the internal main cr oscillator ?0.50.6ma i crl current consumption for the internal sub-cr oscillator oscillating at 100 khz ?2072a
mb95220h series ds07-12626-2e 27 4. ac characteristics (1) clock timing (v cc = 2.4 v to 5.5 v, v ss = 0.0 v, t a = - 40 c to + 85 c) (continued) parameter symbol pin name condition value unit remarks min typ max clock frequency f ch x0, x1 ? 1 ? 16.25 mhz when the main oscillation circuit is used x0, hclk1, hclk2 x1 open 1 ? 12 mhz when the main external clock is used x0, x1, hclk1, hclk2 ? 1 ? 32.5 mhz f crh ?? 9.7 10 10.3 mhz when the main internal clock is used 2.4 v vcc < 5.5 v(0 c t a 40 c) 7.76 8 8.24 mhz 0.97 1 1.03 mhz 9.5 10 10.5 mhz when the main internal clock is used 2.4 v vcc < 5.5 v (-40 c t a < 0 c, 40 c < t a 85 c) 7.6 8 8.4 mhz 0.95 1 1.05 mhz f cl x0a, x1a ? ? 32.768 ? khz when the sub oscillation circuit is used ? 32.768 ? khz when the sub-external clock is used f crl ? ? 50 100 200 khz when the sub-internal cr clock is used clock cycle time t hcyl x0, x1 ? 61.5 ? 1000 ns when the main oscillation circuit is used x0, hclk1, hclk2 x1 open 83.4 ? 1000 ns when the external clock is used x0, x1, hclk1, hclk2 ? 30.8 ? 1000 ns t lcyl x0a, x1a ? ? 30.5 ? s when the subclock is used
mb95220h series 28 ds07-12626-2e (continued) (v cc = 2.4 v to 5.5 v, v ss = 0.0 v, t a = - 40 c to + 85 c) parameter symbol pin name condition value unit remarks min typ max input clock pulse width t wh1 t wl1 x0, hclk1, hclk2 x1 open 33.4 ? ? ns when the external clock is used, the duty ratio should range between 40% and 60%. x0, x1, hclk1, hclk2 ? 12.4 ? ? ns t wh2 t wl2 x0a ? ? 15.2 ? s input clock rise time and fall time t cr t cf x0, hclk1, hclk2 x1 open ? ? 5 ns when the external clock is used x0, x1, hclk1, hclk2 ???5ns internal cr oscillation start time t crhwk ????8 0 s when the main internal cr clock is used t crlwk ????1 0 s when the sub-internal cr clock is used
mb95220h series ds07-12626-2e 29 x0, x1, hclk1, hclk2 0.8 v cc 0.2 v cc 0.2 v cc 0.8 v cc t wh1 t wl1 0.2 v cc t hcyl t cr t cf when a cry stal oscillator or a cer amic oscillator is used when the external clock is used x0 x1 x0 x1 f ch f ch when the external clock is used (x1 is open) x0 x1 open f ch ? figure of main clock input port external connection x0a 0.8 v cc 0.2 v cc 0.2 v cc 0.8 v cc t wh2 t wl2 0.2 v cc t lcyl t cr t cf when a cry stal oscillator or a cer amic oscillator is used when the external clock is used x0a x1a x0a x1a open f cl f cl ? figure of subclock input port external connection
mb95220h series 30 ds07-12626-2e (2) source clock/machine clock (v cc = 5.0 v10%, v ss = 0.0 v, t a = - 40 c to + 85 c) *1: this is the clock before it is divided according to the division ratio set by the machine clock division ratio selection bits (sycc : div1 and div0) . this source clock is divi ded to become a machine clock according to the division ratio set by the machine clock division ratio selection bits (sycc : div1 and div0) . in addition, a source clock can be selected from the following. ? main clock divided by 2 ? main cr clock ? subclock divided by 2 ? sub-cr clock divided by 2 (continued) parameter symbol pin name value unit remarks min typ max source clock cycle time* 1 (clock before division) t sclk ? 61.5 ? 2000 ns when the main external clock is used min: f ch = 32.5 mhz, divided by 2 max: f ch = 1 mhz, divided by 2 100 ? 1000 ns when the main cr clock is used min: f crh = 10 mhz max: f crh = 1 mhz ?61?s when the sub-oscillation clock is used f cl = 32.768 khz, divided by 2 ?20?s when the sub-oscillation clock is used f crl = 100 khz, divided by 2 source clock frequency f sp ? 0.5 ? 16.25 mhz when the main oscillation clock is used 1 ? 10 mhz when the main cr clock is used f spl ? 16.384 ? khz when the sub-oscillation clock is used ?50?khz when the sub-cr clock is used f crl = 100 khz, divided by 2 machine clock cycle time* 2 (minimum instruction execution time) t mclk ? 61.5 ? 32000 ns when the main oscillation clock is used min: f sp = 16.25 mhz, no division max: f sp = 0.5 mhz, divided by 16 100 ? 16000 ns when the main cr clock is used min: f sp = 10 mhz max: f sp = 1 mhz, divided by 16 61 ? 976.5 s when the sub-oscillation clock is used min: f spl = 16.384 khz, no division max: f spl = 16.384 khz, divided by 16 20 ? 320 s when the sub-cr clock is used min: f spl = 50 khz, no division max: f spl = 50 khz, divided by 16 machine clock frequency f mp ? 0.031 ? 16.25 mhz when the main oscillation clock is used 0.0625 ? 10 mhz when the main cr clock is used f mpl 1.024 ? 16.384 khz when the sub- oscillation clock is used 3.125 ? 50 khz when the sub-cr clock is used f crl = 100 khz
mb95220h series ds07-12626-2e 31 (continued) *2: this is the operating clock of the microcontroller. a machine clock can be selected from the following. ? source clock (no division) ? source clock divided by 4 ? source clock divided by 8 ? source clock divided by 16
mb95220h series 32 ds07-12626-2e f ch (main oscillation) f crh (internal main cr clock) f cl (sub-oscillation) f crl (internal sub- cr clock) sclk (source clock) mclk (machine clock) clock mode select bits (sycc2: rcs1, rcs0) division circuit x x x x 1 1/4 1/8 1/16 divided by 2 divided by 2 divided by 2 ? schematic diagram of the clock generation block operating voltage (v) a/d converter operation range 5.5 5.0 4.0 3.5 3.0 2.4 16 khz 3 mhz 10 mhz 16.25 mhz source clock frequency (f sp /f spl ) operating voltage (v) a/d converter operation range 5.5 5.0 4.0 3.5 3.0 2.9 16 khz 3 mhz 10 mhz 16.25 mhz source clock frequency (f sp ) ? operating voltage - operating frequency (when t a = -40 c to + 85 c) mb95220h (without the on-chip debug function) ? operating voltage - operating frequency (when t a = -40 c to + 85 c) mb95220h (with the on-chip debug function)
mb95220h series ds07-12626-2e 33 (3) external reset (v cc = 5.0 v10%, v ss = 0.0 v, t a = - 40 c to + 85 c) *1: see ? (2) source clock/machine clock? for t mclk . *2: the oscillation time of an oscillator is the time for it to reach 90% of its amplitude. the crystal oscillator has an oscillation time of between several ms and tens of ms. the ceramic oscilla tor has an oscillation time of between hundreds of s and several ms. the external clock has an oscillation time of 0 ms. the cr oscillator clock has an oscillation time of between several s and several ms. parameter symbol value unit remarks min max rst ?l? level pulse width t rstl 2 t mclk * 1 ? ns in normal operation oscillation time of the oscillator* 2 + 100 ?s in stop mode, subclock mode, sub-sleep mode, and watch mode 100 ? s in timebase timer mode 0.2 v cc rst 0.2 v cc t rstl t rstl 0.2 v cc 0.2 v cc 100 s x0 internal operating clock 90% of amplitude oscillation time of oscillator oscillation stabilization wait time execute instruction internal reset rst ? in normal operation ? in stop mode, subclock mode, subs leep mode, watch mode and power-on
mb95220h series 34 ds07-12626-2e (4) power-on reset (v ss = 0.0 v, t a = - 40 c to + 85 c) note: a sudden change of power supply voltage may activate the power-on reset function. when changing the power supply voltage during the operation, set the slope of rising to a value below within 30 mv/ms as shown below. parameter symbol condition value unit remarks min max power supply rising time t r ??50ms power supply cutoff time t off ? 1 ? ms wait time until power-on 0.2 v 0.2 v t off t r 2.5 v 0.2 v v cc v cc 2.3 v v ss hold condition in stop mode set the slope of rising to a value below 30 mv/ms.
mb95220h series ds07-12626-2e 35 (5) peripheral input timing (v cc = 5.0 v10%, v ss = 0.0 v, t a = - 40 c to + 85 c) * see ?(2) source clock/machine clock? for t mclk . parameter symbol pin name value unit min max peripheral input ?h? pulse width t ilih int02 to int07, ec0 2 t mclk * ?ns peripheral input ?l? pulse width t ihil 2 t mclk * ?ns int02 to int07, ec0 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc t ilih t ihil
mb95220h series 36 ds07-12626-2e (6) lin-uart timing (available only in MB95F222H/f222k/f223h/f223k) sampling is executed at the ri sing edge of the sampling clock * 1 , and serial clock delay is disabled * 2 . (escr register:sces bit = 0, eccr register:scde bit = 0) (v cc = 5.0 v 10%, av ss = v ss = 0.0 v, t a = - 40 c to + 85 c) *1: there is a function used to choose whether the sampling of reception data is performed at a rising edge or a falling edge of the serial clock. *2: the serial clock delay function is a function used to dela y the output signal of the serial clock for half the clock. *3: see ?(2) source clock/machine clock? for t mclk . parameter symbol pin name condition value unit min max serial clock cycle time t scyc sck internal clock operation output pin: c l = 80 pf +1 ttl 5 t mclk * 3 ?ns sck sot delay time t slovi sck, sot -95 +95 ns valid sin sck t ivshi sck, sin t mclk * 3 + 190 ? ns sck valid sin hold time t shixi sck, sin 0 ? ns serial clock ?l? pulse width t slsh sck external clock operation output pin: c l = 80 pf +1 ttl 3 t mclk * 3 ? t r ?ns serial clock ?h? pulse width t shsl sck t mclk * 3 + 95 ? ns sck sot delay time t slove sck, sot ? 2 t mclk * 3 + 95 ns valid sin sck t ivshe sck, sin 190 ? ns sck valid sin hold time t shixe sck, sin t mclk * 3 + 95 ? ns sck fall time t f sck ? 10 ns sck rise time t r sck ? 10 ns
mb95220h series ds07-12626-2e 37 0.8 v0 . 8 v 2.4 v t slovi t ivshi t shixi 2.4 v 0.8 v sck sot sin 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc t scyc ? internal shift clock mode 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc t slove t ivshe t shixe 2.4 v 0.8 v sck sot sin 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc t slsh t shsl t r 0.8 v cc t f ? external shift clock mode
mb95220h series 38 ds07-12626-2e sampling is executed at the falling edge of the sampling clock * 1 , and serial clock delay is disabled * 2 . (escr register:sces bit = 1, eccr register:scde bit = 0) (v cc = 5.0 v10%, v ss = 0.0 v, t a = - 40 c to + 85 c) *1: there is a function used to choose whether the sampling of reception data is performed at a rising edge or a falling edge of the serial clock. *2: the serial clock delay function is a function used to dela y the output signal of the serial clock for half the clock. *3: see ?(2) source clock/machine clock? for t mclk . parameter symbol pin name condition value unit min max serial clock cycle time t scyc sck internal clock operation output pin: c l = 80 pf +1 ttl 5 t mclk * 3 ?ns sck sot delay time t shovi sck, sot -95 +95 ns valid sin sck t ivsli sck, sin t mclk * 3 + 190 ? ns sck valid sin hold time t slixi sck, sin 0 ? ns serial clock ?h? pulse width t shsl sck external clock operation output pin: c l = 80 pf +1 ttl 3 t mclk * 3 ? t r ?ns serial clock ?l? pulse width t slsh sck t mclk * 3 + 95 ? ns sck sot delay time t shove sck, sot ? 2 t mclk * 3 + 95 ns valid sin sck t ivsle sck, sin 190 ? ns sck valid sin hold time t slixe sck, sin t mclk * 3 + 95 ? ns sck fall time t f sck ? 10 ns sck rise time t r sck ? 10 ns
mb95220h series ds07-12626-2e 39 0.8 v 2.4 v 2.4 v t shovi t ivsli t slixi 2.4 v 0.8 v sck sot sin 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc t scyc ? internal shift clock mode 0.2 v cc 0.2 v cc 0.2 v cc 0.8 v cc t shove t ivsle t slixe 2.4 v 0.8 v sck sot sin 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc t shsl t slsh t f 0.8 v cc t r ? external shift clock mode
mb95220h series 40 ds07-12626-2e sampling is executed at the ri sing edge of the sampling clock * 1 , and serial clock delay is enabled * 2 . (escr register:sces bit = 0, eccr register:scde bit = 1) (v cc = 5.0 v10%, v ss = 0.0 v, t a = - 40 c to + 85 c) *1: there is a function used to choose whether the sampling of reception data is performed at a rising edge or a falling edge of the serial clock. *2: the serial clock delay function is a function that delays the output signal of the serial clock for half clock. *3: see ?(2) source clock/machine clock? for t mclk . parameter symbol pin name condition value unit min max serial clock cycle time t scyc sck internal clock operation output pin: c l = 80 pf +1 ttl 5 t mclk * 3 ?ns sck sot delay time t shovi sck, sot -95 +95 ns valid sin sck t ivsli sck, sin t mclk * 3 + 190 ? ns sck valid sin hold time t slixi sck, sin 0 ? ns sot sck delay time t sovli sck, sot ? 4 t mclk * 3 ns 2.4 v 0.8 v0 . 8 v t s hovi t s ovli t ivsli t slixi 2.4 v 0.8 v 2.4 v 0.8 v sck sot sin 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc t scyc
mb95220h series ds07-12626-2e 41 sampling is executed at the falling edge of the sampling clock * 1 , and serial clock delay is enabled * 2 . (escr register:sces bit = 1, eccr register:scde bit = 1) (v cc = 5.0 v10%, v ss = 0.0 v, t a = - 40 c to + 85 c) *1:there is a function used to choose whether the sampli ng of reception data is performed at a rising edge or a falling edge of the serial clock. *2: the serial clock delay function is a function that delays the output signal of the serial clock for half clock. *3: see ?(2) source clock/machine clock? for t mclk . parameter symbol pin name condition value unit min max serial clock cycle time t scyc sck internal clock operation output pin: c l = 80 pf +1 ttl 5 t mclk * 3 ?ns sck sot delay time t slovi sck, sot -95 +95 ns valid sin sck t ivshi sck, sin t mclk * 3 + 190 ? ns sck valid sin hold time t shixi sck, sin 0 ? ns sot sck delay time t sovhi sck, sot ? 4 t mclk * 3 ns 0.8 v 2.4 v 2.4 v t s lovi t s ovhi t ivshi t shixi 2.4 v 0.8 v 2.4 v 0.8 v sck sot sin 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc t scyc
mb95220h series 42 ds07-12626-2e (7) low-voltage detection (v ss = 0.0 v, t a = - 40 c to + 85 c) parameter symbol value unit remarks min typ max release voltage v dl + 2.52 2.7 2.88 v at power supply rise detection voltage v dl ? 2.42 2.6 2.78 v at power supply fall hysteresis width v hys 70 100 ? mv power supply start voltage v off ??2.3v power supply end voltage v on 4.9 ? ? v power supply voltage change time (at power supply rise) t r 1??s slope of power supply that the reset release signal generates ? 3000 ? s slope of power supply that the reset release signal generates within the rating (v dl+ ) power supply voltage change time (at power supply fall) t f 300 ? ? s slope of power supply that the reset detection signal generates ? 300 ? s slope of power supply that the reset detection signal generates within the rating (v dl- ) reset release delay time t d1 ??300s reset detection delay time t d2 ??20s
mb95220h series ds07-12626-2e 43 v hys t d2 t d1 t r t f v cc intern al reset signal v on v off v dl+ v dl- time time
mb95220h series 44 ds07-12626-2e 5. a/d converter (1) a/d converter electrical characteristics (v cc = 4.0 v to 5.5 v, v ss = 0.0 v, t a = - 40 c to + 85 c) parameter symbol value unit remarks min typ max resolution ? ? ? 10 bit total error -3 ? +3 lsb linearity error -2.5 ? +2.5 lsb differential linear error -1.9 ? +1.9 lsb zero transition voltage v ot v ss ? 1.5 lsb v ss + 0.5 lsb v ss + 2.5 lsb v full-scale transition voltage v fst v cc ? 4.5 lsb v cc ? 2 lsb v cc + 0.5 lsb v compare time ? 0.9 ? 16500 s 4.5 v v cc 5.5 v 1.8 ? 16500 s 4.0 v v cc < 4.5 v sampling time ? 0.6 ? s 4.5 v v cc 5.5 v, with external impedance < 5.4 k 1.2 ? s 4.0 v v cc 4.5 v, with external impedance < 2.4 k analog input current i ain -0.3 ? +0.3 a analog input voltage v ain v ss ?v cc v
mb95220h series ds07-12626-2e 45 (2) notes on using the a/d converter ? external impedance of anal og input and its sampling time ? the a/d converter has a sample and hold circuit. if the external impedance is too high to keep sufficient sampling time, the analog voltage charged to the capacitor of the internal sample and hold circuit is insufficient, adversely affecting a/d conversion precision. therefor e, to satisfy the a/d conversion precision standard, considering the relationship between the external im pedance and minimum sampling time, either adjust the register value and operating frequency or decrease the ex ternal impedance so that the sampling time is longer than the minimum value. in addition, if sufficient sampling time cannot be secured, connect a capacitor of about 0.1 f to the analog input pin. ? a/d conversion error as |v cc ?v ss | decreases, the a/d conversion error increases proportionately. compar ator analog input du ring sa mpling: on note: the v alues a re reference v alues . ~ ~ ~ ~ < = < = 4.5 v v cc 5.5 v : r 1.95 k (ma x), c 17 pf (max) ~ ~ ~ ~ < = < 4.0 v v cc 4.5 v : r 8.98 k (ma x), c 17 pf (max) r c ? analog input equivalent circuit [extern al impedance = 0 k to 100 k ] extern al impedance [k] extern al impedance [k] minim um sampling time [s] minim um sampling time [s] [extern al impedance = 0 k to 20 k ] 100 90 80 70 60 50 40 30 20 10 0 20 18 16 14 12 10 8 6 4 2 0 02468 10 12 14 1 02 3 4 (v cc > = 4.5 v) (v cc > = 4.0 v) (v cc > = 4.5 v) (v cc > = 4.0 v) ? relationship between external im pedance and minimum sampling time
mb95220h series 46 ds07-12626-2e (3) definitions of a/d converter terms ? resolution it indicates the level of analog variation that can be distinguished by the a/d converter. when the number of bits is 10, an alog voltage can be divided into 2 10 = 1024. ? linearity error (unit: lsb) it indicates how much an actual conversion va lue deviates from the straight line connecting the zero transition point (?00 0000 0000? ?00 0000 0001?) of a device to the full-scale transition point (?11 1111 1111? ?11 1111 1110?) of the same device. ? differential linear error (unit : lsb) it indicates how much the input voltage required to ch ange the output code by 1 lsb deviates from an ideal value. ? total error (unit: lsb) it indicates the difference between an actual value and a theoretical value. the error can be caused by a zero transition error, a full-scale transition errors, a linearity error, a quantum error, or noise. (continued) v ss v fst ideal i/o char a cteristics v cc 001 002 003 004 3fd 3fe 3ff digital output digital output 2 lsb v ot 1 lsb 0.5 lsb to t al error analog input analog input 001 002 003 004 3fd 3fe 3ff actua l conversion char a cteristic ideal char a cteristic actua l conversion char a cteristic n v nt : a/d converter digit al output v alue : volt age at which the digital output tr ansits from (n - 1) to n {1 lsb x (n-1) + 0.5 lsb} v nt v ss v cc to t al error of digital output n v nt - {1 lsb x (n - 1) + 0.5 lsb} 1 lsb [lsb] = v cc - v ss 1024 (v) 1 lsb =
mb95220h series ds07-12626-2e 47 (continued) zero tr ansition error linea rity error full-scale tr ansition error 001 002 003 004 3fd 3fe 3ff digital output differenti al linear error of digital output n v (n+1)t - v nt 1 lsb - 1 = linea rity error of digital output n v nt - {1 ls b x n + v ot } 1 lsb = digital output analog input 001 002 3fc 3fd 003 3fe 3ff 004 actua l conversion char a cteristic ideal char a cteristic actua l conversion char a cteristic v ot (measurement v alue) actua l conversion char a cteristic actua l conversion char a cteristic v fst (measurement v alue) v ss v cc analog input v ss v cc digital output analog input v ss v cc ideal char a cteristic {1 ls b x n + v ot } actua l conversion char a cteristic ideal char a cteristic actua l conversion char a cteristic v ot (measurement v alue) v fst (measurement v alue) v nt differenti al linea rity error n-2 n-1 n n+1 digital output analog input v ss v cc actua l conversion char a cteristic ideal char a cteristic v nt actua l conversion char a cteristic v (n+1)t n v nt : a/d converter digit al output v alue : volt age at which the digital output tr ansits from (n - 1) to n v ot (ideal v alu e) = v ss + 0.5 lsb [v] v fst (ideal v alu e) = v cc - 2 lsb [v]
mb95220h series 48 ds07-12626-2e 6. flash memory program/erase characteristics *1: t a = +25 c, v cc = 5.0 v, 100000 cycles *2: t a = +85 c, v cc = 4.5 v, 100000 cycles *3: this value is converted from the result of a technolo gy reliability assessment. (the value is converted from the result of a high temperature accelerated test by usi ng the arrhenius equation with the average temperature being +85 c) . parameter value unit remarks min typ max chip erase time ? 1* 1 15* 2 s 00 h programming time prior to erasure is excluded. byte programming time ? 32 3600 s sy stem-level overhead is excluded. erase/program voltage 9.5 10 10.5 v the erase/program voltage must be applied to the rst pin in erase/program. erase/program cycle ? 100000 ? cycle power supply voltage at erase/ program 4.5 ? 5.5 v flash memory data retention time 20* 3 ? ? year average t a = +85 c
mb95220h series ds07-12626-2e 49 sample electrical characteristics ? power supply current ? temperature (continued) i cc - v cc t a =+25c, f mp =2, 4, 8, 10, 16 mhz (divided b y 2) ma in clock mode with the externa l clock oper ating v cc [v] i cc [ma] f mp =16 mhz f mp =10 mhz f mp =8 mhz f mp =4 mhz f mp =2 mhz 2 3 4567 20 15 10 5 0 i cc - t a v cc =5.5 v, f mp =10, 16 mhz (divided b y 2) ma in clock mode with the externa l clock oper ating t a [c] i cc [ma] -50 0 +50 +100 +150 20 15 10 5 0 f mp =16 mhz f mp =10 mhz i ccs - v cc t a =+25c, f mp =2, 4, 8, 10, 16 mhz (divided b y 2) main s leep mode with the externa l clock oper ating v cc [v] i ccs [ma] f mp =8 mhz f mp =10 mhz f mp =16 mhz f mp =4 mhz f mp =2 mhz 2 3 4567 20 15 10 5 0 i ccs - t a v cc =5.5 v, f mp =10, 16 mhz (divided b y 2) main s leep mode with the externa l clock oper ating t a [c] i ccs [ma] -50 0 +50 +100 +150 20 15 10 5 0 f mp =16 mhz f mp =10 mhz i ccl - v cc t a =+25c, f mpl =16 khz (divided b y 2) sub clock mode with the externa l clock oper ating v cc [v] i ccl [a] 2 3 4567 100 75 50 25 0 i ccl - t a v cc =5.5 v, f mpl =16 khz (divided b y 2) sub clock mode with the externa l clock oper ating t a [c] i ccl [a] -50 0 +50 +100 +150 100 75 50 25 0
mb95220h series 50 ds07-12626-2e (continued) i ccls - v cc t a =+25c, f mpl =16 khz (divided b y 2) subs leep mode with the externa l clock oper ating v cc [v] i ccls [a] 2 3 4567 100 75 50 25 0 i ccls - t a v cc =5.5 v, f mpl =16 khz (divided b y 2) subs leep mode with the externa l clock oper ating t a [c] i ccls [a] -50 0 +50 +100 +150 100 75 50 25 0 i cct - v cc t a =+25c, f mpl =16 khz (divided b y 2) clock mode with the extern a l clock oper ating v cc [v] i cct [a] 2 3 4567 100 75 50 25 0 i cct - t a v=5.5 v, f mpl =16 khz (divided b y 2) clock mode with the extern a l clock oper ating t a [c] i cct [a] -50 0 +50 +100 +150 100 75 50 25 0 i cts - v cc t a =+25c, f mp =2, 4, 8, 10, 16 mhz (divided b y 2) timebas e timer mode with the externa l clock oper ating v cc [v] i cts [ma] 2 3 4567 2.0 1.5 1.0 0.5 0.0 f mp =2 mhz f mp =4 mhz f mp =8 mhz f mp =16 mhz f mp =10 mhz i cts - t a v=5.5 v, f mp =10, 16 mhz (divided b y 2) timebas e timer mode with the externa l clock oper ating t a [c] i cts [ma] -50 0 +50 +100 +150 2.0 1.5 1.0 0.5 0.0 f mp =10 mhz f mp =16 mhz
mb95220h series ds07-12626-2e 51 (continued) i cch - v cc t a =+25c, f mpl =(stop) subs top mode wtih the externa l clock stopping v cc [v] i cch [a] 2 3 4567 20 15 10 5 0 i cch - t a v=5.5 v, f mpl =(stop) subs top mode with the externa l clock stopping t a [c] i cch [a] -50 0 +50 +100 +150 20 15 10 5 0 i ccmcr - v cc t a =+25c, f mp =1, 8, 10 mhz (no division) ma in clock mode with the internal ma in cr clock oper ating v cc [v] i ccmcr [ma] 2 3 4567 20 15 10 5 0 f mp =8 mhz f mp =1 mhz f mp =10 mhz i ccmcr - t a v=5.5 v, f mpl =1, 8, 10 mhz (no division) ma in clock mode with the internal ma in cr clock oper ating t a [c] i ccmcr [ma] -50 0 +50 +100 +150 20 15 10 5 0 f mp =1 mhz f mp =8 mhz f mp =10 mhz i ccscr - v cc t a =+25c, f mpl =50 khz (divided b y 2) sub clock mode with the internal sub -cr clock oper ating v cc [v] i ccscr [a] 2 3 4567 200 150 100 50 0 f mpl =50 khz i ccscr - t a v cc =5.5 v, f mpl =50 khz (divided b y 2) sub clock mode with the internal sub -cr clock oper ating t a [c] i ccscr [a] -50 0 +50 +100 +150 200 150 100 50 0 f mpl =50 khz
mb95220h series 52 ds07-12626-2e ? input voltage v ihi - v cc and v ili - v cc t a =+25c v cc [v] v ihi /v ili [v] 2 3 4567 5 4 3 2 1 0 v ihi v ili v ihs - v cc and v ils - v cc t a =+25c v cc [v] v ihs /v ils [v] 2 3 4567 5 4 3 2 1 0 v ils v ihs v ihm - v cc and v ilm - v cc t a =+25c v cc [v] v ihm /v ilm [v] 2 3 4567 5 4 3 2 1 0 v ilm v ihm
mb95220h series ds07-12626-2e 53 ? output voltage (v cc -v oh1 ) - i oh t a =+25c i oh [ma] v cc -v oh1 [v] v cc =2.4 v v cc =2.7 v v cc =3.5 v v cc =4.5 v v cc =5.0 v v cc =5.5 v 0-2-4-6- 8 -10 1.0 0.8 0.6 0.4 0.2 0.0 (v cc -v oh2 ) - i oh t a =+25c i oh [ma] v cc -v oh2 [v] 0-2-4-6- 8 -10 1.0 0.8 0.6 0.4 0.2 0.0 v cc =2.4 v v cc =2.7 v v cc =3.5 v v cc =4.5 v v cc =5.0 v v cc =5.5 v v ol1 - i ol t a =+25c i ol [ma] v ol1 [v] 02468 10 1.0 0.8 0.6 0.4 0.2 0.0 v cc =2.4 v v cc =2.7 v v cc =3.5 v v cc =4.5 v v cc =5.0 v v cc =5.5 v v ol2 - i ol t a =+25c i ol [ma] v ol2 [v] 02 4 6 8 10 12 1.0 0.8 0.6 0.4 0.2 0.0 v cc =2.4 v v cc =2.7 v v cc =3.5 v v cc =4.5 v v cc =5.0 v v cc =5.5 v
mb95220h series 54 ds07-12626-2e ? pull-up r pull - v cc t a =+25c v cc [v] r pull [k] 2 3 456 250 200 150 100 50 0
mb95220h series ds07-12626-2e 55 mask options ordering information no. part number MB95F222H mb95f223h mb95f222k mb95f223k selectable/fixed fixed fixed 1 low-voltage detection reset ? with low-voltage detection reset ? without low-voltage detection reset without low-voltage detection reset with low-voltage detection reset 2 reset ? with dedicated reset input ? without dedicated reset input with dedicated reset input wit hout dedicated reset input part number package MB95F222Hph-g-sne2 mb95f222kph-g-sne2 mb95f223hph-g-sne2 mb95f223kph-g-sne2 16-pin plastic dip (dip-16p-m06) MB95F222Hpf-g-sne1 mb95f222kpf-g-sne1 mb95f223hpf-g-sne1 mb95f223kpf-g-sne1 16-pin plastic sop (fpt-16p-m06)
mb95220h series 56 ds07-12626-2e package dimensions please confirm the latest package dimension by following url. http://edevice.fujitsu.com/package/en-search/ (continued) 16-pin plas tic dip le a d pitch 2.54 mm s e a ling method plastic mold 16-pin plas tic dip (dip-16p-m06) (dip-16p-m06) c 2006-2008 fujit s u microelectronics limited d16125s-c-1-2 0.25 0.05 (.010 .002) 15 max .770 ? .012 +.008 ? 0.30 +0.20 19.55 index 0.50(.020) min typ. 2.54(.100) (.018 .003) 0.46 0.08 3.00(.118)min 4.36(.172)max 1.52 .060 ? 0 +.012 ? 0 +0.30 max 1.27(.050) typ. 7.62(.300) 6.35 0.25 (.250 .010) .039 0.99 +.012 ? 0 +0.30 ? 0 dimens ion s in mm (inche s ). note: the va l u e s in pa renthes e s a re reference va l u e s
mb95220h series ds07-12626-2e 57 (continued) please confirm the latest package dimension by following url. http://edevice.fujitsu.com/package/en-search/ 16-pin plastic s op le a d pitch 1.27 mm p a ck a ge width p a ck a ge length 5.3 10.15 mm lea d s h a pe gu llwing s e a ling method plastic mold mou nting height 2.25 mm max weight 0.20 g code (reference) p-s op16-5.3 10.15-1.27 16-pin plastic sop (fpt-16p-m06) (fpt-16p-m06) c 2002-2008 fujits u microelectronics limited f16015s-c-4-8 0.13(.005) m details of "a" part 7.800.40 5.300.30 (.209.012) (. 307.016) ?.008 +.010 ?0.20 +0.25 10.15 index 1.27(.050) 0.10(.004) 1 8 9 16 0.470.08 (.019.003) ?0.04 +0.03 0.17 .007 +.001 ?.002 "a" 0.25(.010) (stand off) 0~8 (mounting height) 2.00 +0.25 ?0.15 .079 +.010 ?.006 0.500.20 (.020.008) 0.600.15 (.024.006) 0.10 +0.10 ?0.05 ?.002 +.004 .004 .400 * 1 * 2 0.10(.004) dimens ion s in mm (inche s ). note: the v a l u e s in p a renthe s e s a re reference v a l u e s . note 1) * 1 : thes e dimens ions inclu de res in protrusion. note 2) * 2 : these dimensions do not include resin protrusion. note 3 )pin s width a nd pins thickness inclu de pla ting thickness. note 4) pin s width do not inclu de tie bar cu tting rema inder.
mb95220h series 58 ds07-12626-2e main changes in this edition the vertical lines marked in the left side of the page show the changes. page section change results 27 electrical characteristics 4. ac characteristics (1) clock timing changed the remarks. 49 to 54 sample electrical characterist ics added the ?sample electrical characteristics?.
mb95220h series ds07-12626-2e 59 memo
mb95220h series fujitsu microelectronics limited shinjuku dai-ichi seimei bldg ., 7-1, nishishinjuku 2-chome, shinjuku-ku, tokyo 163-0722, japan tel: +81-3-5322-3329 http://jp.fujitsu.com/fml/en/ for further information please contact: north and south america fujitsu microelectronics america, inc. 1250 e. arques avenue, m/s 333 sunnyvale, ca 94085-5401, u.s.a. tel: +1-408-737-5600 fax: +1-408-737-5999 http://www.fma.fujitsu.com/ europe fujitsu microelectronics europe gmbh pittlerstrasse 47, 63225 langen, germany tel: +49-6103-690-0 fax: +49-6103-690-122 http://emea.fujitsu.com/microelectronics/ korea fujitsu microelectronics korea ltd. 206 kosmo tower building, 1002 daechi-dong, gangnam-gu, seoul 135-280, republic of korea tel: +82-2-3484-7100 fax: +82-2-3484-7111 http://kr.fujitsu.com/fmk/ asia pacific fujitsu microelectronics asia pte. ltd. 151 lorong chuan, #05-08 new tech park 556741 singapore tel : +65-6281-0770 fax : +65-6281-0220 http://www.fmal.fujitsu.com/ fujitsu microelectronics shanghai co., ltd. rm. 3102, bund center, no.222 yan an road (e), shanghai 200002, china tel : +86-21-6146-3688 fa x : +86-21-6335-1605 http://cn.fujitsu.com/fmc/ fujitsu microelectronics pacific asia ltd. 10/f., world commerce centre, 11 canton road, tsimshatsui, kowloon, hong kong tel : +852-2377-0226 fax : +852-2376-3269 http://cn.fujitsu.com/fmc/en/ specifications are subject to change without notice. for further information please contact each office. all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with sales representatives before ordering. the information, such as descriptions of f unction and application circuit examples, in this document are presented solely for t he purpose of reference to show examples of operations and uses of fujitsu microelectronics device; fujitsu microelectronics does not warrant proper operation of the device with respect to use based on such information. when you develop equipment incor porating the device based on such information, you must assume any re sponsibility arising out of such use of the information. fujitsu microelectronics assumes no liability for any damages whatsoever arising out of the use of the information. any information in this document, including descriptions of f unction and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of fujitsu microelectroni cs or any third party or does fujitsu microelectronics warrant non-i nfringement of any third-party's intellectual property right o r other right by using such information. fujitsu microelectronics assumes no liability for any infringement of the intellectual property rights or other rights of third parties which w ould result from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and m anufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a ser ious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction con trol in nuclear facility, aircraft flight control, air tr affic control, mass transport control, me dical life support system, missile launch con trol in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). please note that fujitsu microelectronics will not be liable against you and/or any third party for any claims or damages arisi ng in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failure s by incorporating safety design measures into your facility and equi pment such as redundancy, fire protection, and prevention of ov er-current levels and other abnormal operating conditions. exportation/release of any products described in this document may require necessary procedures in accordance with the regulati ons of the foreign exchange and foreign trade control law of japan and/or us export control laws. the company names and brand names herein are the trademarks or registered trademarks of their respective owners. edited: sales promotion department

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